1. Field of the Invention
This invention relates to a thin-film semiconductor device which is applicable, for example, to an active matrix type flat panel display and to a method for manufacturing the thin-film semiconductor device.
2. Description of the Related Art
The technique for utilizing semiconductor thin films is an important technology for forming semiconductor devices such as a thin film transistor (TFT), a contact type sensor, a photoelectric conversion device, etc. Thin film transistor is a field-effect transistor of MOS (MIS) structure and is applied to a flat panel display such as a liquid crystal display device (for example, P. G. LeComber, W. E. Spear and A. Ghaith, “Amorphous-Silicon Field-Effect Device and Possible Application”, Electronics Letter, Vol. 15, No. 6, pp. 179-181, March 1979).
A liquid crystal display device is characterized in that it is generally thin in thickness, light in weight and low in power consumption, and that it is easy in displaying colors. In view of these characteristics, the liquid crystal display device is widely used as a personal computer or as a display for various kinds of mobile information terminals. When the liquid crystal display device is of active matrix type, the thin film transistor is installed therein as a pixel switching device.
The active layer (carrier mobile layer) of the thin film transistor is formed of a silicon thin film for example. This silicon thin film can be classified into amorphous silicon (a-Si) and polycrystalline silicon (non-monocrystalline silicon) having crystal phases. The polycrystalline silicon is mainly constituted by poly-silicon (Poly-Si), and microcrystal silicon (μc-Si) is also known as a kind of polycrystalline silicon. The materials for the semiconductor thin film include, other than silicon, for example SiGe, SiO, CdSe, Te, CdS, etc.
The carrier mobility of polycrystalline silicon is about 10-100 times as large as the carrier mobility of amorphous silicon. From this characteristic of polycrystalline silicon, it is evident that the polycrystalline silicon is very excellent for use as a semiconductor thin film material for a switching device.
In recent years, because of high-speed in operation, the thin film transistor wherein an active layer is formed of polycrystalline silicon is used as has been noticed as a switching device which is employed as various kinds of logic circuits such, for example, as a domino circuit and CMOS transmission gate. These logic circuits are needed as the driving circuit of a liquid crystal display device or of an electroluminescence display device, a multiplexer, EPROM, EEPROM, CCD, RAM, etc.
Herein, the conventional representative process for forming a polycrystalline silicon thin film will be explained. In this process, an insulating substrate such as a glass substrate is prepared at first and then a silicon oxide film (SiO2) for example is formed as an under coat layer (or a buffer layer) on the insulating substrate. Further, an amorphous silicon (a-Si) film is formed to a thickness of about 50 nm-100 nm as a semiconductor thin film on this under coat layer. Thereafter, the amorphous silicon film is subjected to dehydrogenation treatment for decreasing the hydrogen concentration in the amorphous silicon film. Then, by means of excimer laser crystallization method, etc., the fusion/recrystallization of the amorphous silicon film is performed. More specifically, excimer laser is irradiated to the amorphous silicon film, thereby converting the amorphous silicon into polycrystalline silicon.
The thin film transistor layer formed on a glass substrate in this manner is subjected to a fine patterning technique, a thin film formation technique, an impurity doping technique, a cleaning technique, a heat treatment technique, etc. which are now employed in the field of IC (LSI). These steps are repeated to form a desired device/circuit.
At present, a semiconductor thin film of polycrystalline silicon as described above is employed as an active layer of an n-channel or p-channel type thin film transistor. In this case, the field effect mobility (the mobility of electrons or holes by the electric field effect) of the thin film transistor becomes about 100-150 cm2/Vsec in the case of the n-channel type thin film transistor and about 100 cm2/Vsec in the case of the p-channel type thin film transistor. By making use of the thin film transistor as described above, driving circuits such as a signal line driving circuit and a scanning line driving circuit can be formed, together with a pixel switching device, on the same substrate, thus obtaining a driving circuit-integrated display device and thereby making it possible to reduce the manufacturing cost of the display device.
As described above, by promoting the miniaturization of the thin-film semiconductor device, it has been made possible to enhance the performance of device/circuit as well as the reliability of the system. However, the thin-film semiconductor device in itself has many factors that degrade the reliability thereof. These factors include a phenomenon called “hot carrier phenomenon” originating from the physical properties of device in addition to factors originating from the materials employed therein (such as disconnection due to the fatigue or corrosion of metal interconnects, dielectric breakdown, the variation in characteristics of device due to contamination (by Na, etc.), etc.).
Namely, the electron that has been accelerated by the electric field in a channel is caused to impinge against the lattice of Si as the energy of the electron is increased beyond the energy of band gap (1.1 eV), thereby generating an electron-hole pair (impact ionization). On this occasion, the electron is attracted by the gate voltage VG and enabled to jump into the gate oxide film even if the electron is not necessarily provided with a high energy exceeding the potential barrier (about 3.1 eV) of Si—SiO2. Some of the electrons are captured in this oxide film and permitted to remain therein as an electric charge. This not only causes the Vth of a transistor to shift toward the positive direction but also cause the mutual conductance gm to decrease. When the electric field inside the element is high, the electron existed in the channel is enabled to directly jump into the gate oxide film. The problem related to the reliabilities as described above is called “hot-carrier effect”, presenting an important factor which obstructs the miniaturization of the device.
This hot-carrier effect is caused to generate by a high electric field. Accordingly, it is generally recognized that a method of providing an n-type (p-type) region of low dope concentration in the vicinity of the drain exhibiting a highest electric field to thereby alleviate the electric field is effective in suppressing the hot-carrier effect. A device which has been figured out to cope with this problem is a structure called “lightly doped drain (LDD)”, which is also effective in the p-type region.
This LDD structure is generally produced as follows. First of all, by making use of a gate electrode as a mask, an n-type impurity ion and a p-type impurity ion are respectively implanted into a semiconductor thin film under a low doping condition {n−layer (p−-layer)}. Subsequently, an SiO2 film is deposited all over the surface of the semiconductor thin film and then the entire surface of the SiO2 film is uniformly etched by means of oriented dry etching, thereby leaving a sidewall spacer formed of the SiO2 film on the sidewall of the gate electrode. By making use of this spacer as a mask, ions are implanted into the semiconductor thin film under the condition where the doping concentration can be made relatively high, thereby forming n+-layer (p+-layer) in the semiconductor thin film. Since the impact ionization phenomenon depends strongly on the intensity of electric field, it is possible to improve the breakdown voltage even if the alleviation in intensity of electric field is only 10%.
Meanwhile, it is generally considered necessary to perform a heat treatment of 1000° C. or more in order to activate the n-type (p-type) impurities that have been implanted into the thin film as described above so as to provide the impurities with the function of conductive carrier. However, if this heat treatment is to be applied to a glass substrate, it would be imperative to perform the heat treatment at a temperature of not higher than 600° C. in viewpoint of the heat resistance of the glass substrate. The characteristics to be obtained from the heat treatment performed under such a condition (a low temperature process) are extremely poor (deterioration of the characteristics of transistor), hence limiting the kinds of devices to which such a low temperature heat treatment can be appropriately applied. Therefore, it is now desired to develop an alternate technique which is capable of achieving sufficiently high activations even with such a low temperature process.
Incidentally, the electric characteristics of the existing thin film transistor are not so excellent that makes it possible to integrate a DA converter which is designed to convert digital picture data into analog picture signals with a signal processing circuit, such as a gate array, which is designed to process digital picture data on the same substrate of a display device. In order to realize such an integrated structure, a sufficient magnitude of current driving capability which is three to five times as high as that of the existing thin film transistor is considered to be required. Furthermore, the field effect mobility of about 300 cm2/Vsec is considered to be required. In order to provide the display device with an enhanced function and an enhanced added value, it is required to further enhance the electric properties of the thin film transistor. If a static memory including a thin film transistor is to be applied to each of pixels in order to enable each pixel to have a memory function for example, the thin film transistor is required to have electric properties which are comparative to those of a single-crystal semiconductor.
Because of these reasons, there are now extensively conducted many studies on how to approach the crystallinity of the thin film semiconductor to that of single crystal as well as on important subject matters, i.e. how to repair the amorphous layer or defects that have been caused to occur due to the doping of impurities or how to enhance the crystallinity by making use of recrystallization technique and activation technique.
As described above, one of the important factors which determine the electric properties of the thin film transistor resides in how to enhance the activation factor of n-type (p-type) impurities that have been doped (ion implantation or ion doping) into a silicon thin film formed on a glass substrate. Since a fairly long time ago, this activation factor strongly depends on the temperature and time of heat treatment to be performed subsequent to the doping of impurities. It has been reported however that in the cases of the impurity implantation (doping) and heat treatment that have been employed in the conventional manufacturing process of a thin film transistor {for example, furnace annealing: 600° C./two-hour heat treatment; or quick heating by way of the convection using a high-temperature gas injection (so-called pseudo-RTA (rapid thermal annealing)): 600° C./five-minute heat treatment}, it is impossible to achieve an activation factor of even 25% (for example, T. Ito, T. Iinuma, A. Murakoshi, H. Akutsu, K. Suguro, T. Arikado, K. Okumura, M. Yoshida, T. Owada, Y. Imaoka, H. Murayama and T. Kusuda; “10-15 nm Ultrashallow Junction Formation by Flash-Lamp Annealing”; Jpn. J. Appl. Phys. Vol. 41, Part 1, No. 4B, April 2002, pp. 2394-2398).
In order to further enhance the activation factor of the impurities that have been doped, it is now considered increasingly important to enhance the quality of polycrystalline silicon, i.e. the film quality of the starting material (film quality before the heat treatment thereof) (through the improvement of recrystallization technique) and, at the same time, to find out a method for improving the crystallinity of semiconductor thin film rather than depending on the conventional method of adjusting the manner of applying the temperature and time of heat treatment based on the aforementioned concept {namely, furnace annealing: 600° C./two-hour heat treatment; or quick heating by way of the convection using a high-temperature gas injection (so-called pseudo-RTA (rapid thermal annealing)): 600° C./five-minute heat treatment}.
With respect to the method of enhancing the activation factor of impurities, there has been tried the application of RTP (Rapid Thermal Processing) {which is also called RTA (Rapid Thermal Annealing)} process, wherein RTA using a tungsten halogen lamp has been tried at first. However, due to an insufficient overlapping between the radiation spectrum of the lamp and the absorption wavelength of silicon, it was impossible to realize the effective absorption of light, resulting in the failure to achieve effective heating for temperature rise.
Recently, in the field of IC (LSI), a quick heating system using a xenon flash lamp has been studied as a light source for enabling more effective heating (for example, T. Ito, T. Iinuma, A. Murakoshi, H. Akutsu, K. Suguro, T. Arikado, K. Okumura, M. Yoshida, T. Owada, Y. Imaoka, H. Murayama and T. Kusuda; “10-15 nm Ultrashallow Junction Formation by Flash-Lamp Annealing”; Jpn. J. Appl. Phys. Vol. 41, Part 1, No. 4B, April 2002, pp. 2394-2398).
Meanwhile, as described above, the study of laser recrystallization process for converting amorphous silicon into polycrystalline silicon by making use of laser has been performed since a fairly long time ago, and, hence, the study on the laser activation using laser has been also made for a long time. However, these methods are accompanied with a problem in the application thereof to actual devices that, due to the influence of an underlying pattern or due to the influence of gate electrode, it is difficult to carry out uniform heating, thereby making these methods unsuitable for practical use.
Further, in the case of the miniaturized devices beginning from a submicron TFT, increased thinning of a Si active layer as well as increased miniaturization of contact size is assumed to be required. In the case of the conventional source/drain layers, they are formed by the heat treatment of a Si layer which has been doped in advance with impurities, wherein the impurities are activated at a temperature of 600° C. In the trial experiments using an SOI substrate, it has been found possible to realize a sheet resistance of 130 Ω/□ with n+ and 522 Ω/□ with p+. However, when the heat treatment is performed at a lower temperature, the activation factor of impurities would be inevitably deteriorated, unavoidably resulting in an increased electric resistance. In the case of a TFT of 0.5 μm rule, it has been estimated, from the results of the trial experiments performed on a transistor of the same size as that of the TFT according to the semiconductor manufacturing process of the prior art, that the sheet resistance of source/drain layers is required to be not higher than 100 Ω/□ and the contact resistance is required to be not higher than 1×10−6 Ωcm2. Therefore, in order to realize these targets, it is indispensable to introduce a new technique for realizing these targets.
With respect to the technique for realizing low resistance source/drain layers, it is conceivable to apply a siliciding technique which has been actually employed in the field of semiconductor (IC, LSI). In the experiments conducted by the present inventors, the formation of TixSiy and NixSiy on an insulating substrate was tried and the performances obtained therefrom were confirmed.
On the other hand, in the case of a micro-device which is capable of achieving a high-speed operation at a low voltage, it is indispensable to increasingly lower the contact resistance. Generally, in order to lower the contact resistance as well as the electric resistance of source/drain regions, they are coped with a high-temperature heat treatment at an applicable upper limit while taking into consideration the combinations among the materials in each step.
In the process for forming a TFT on a glass substrate, the activation of the doped impurities is generally executed by way of a low temperature process of 600° C. in view of overcoming the problem of the heat resistance of glass. Further, since the material constituting the source/drain layers is Si, it is required to develop novel materials, construction and forming method so as to cope with the further lowering of electric resistance. Especially, supposing that high-frequency elements for communication are to be integrally mounted, it would be imperative to further lower the electric resistance of interconnects together with the lowering of the contact resistance.
In the IC manufacturing process, it is possible to apply a high-temperature process of 600° C. or more, so that a method of forming a low resistance thin film such as a high-melting point metal film or a high-melting point silicide film on the source/drain diffusion regions is already employed in some kinds of device. This process is called “salicide process” (SALICIDE: Self-Aligned Silicide) which is a process wherein silicide film is formed on the source/drain diffusion regions in a self-aligned manner (for example, S. M. Sze, VLSI Technology, second edition, McGROW-HILL INTERNATIONAL EDITIONS, 1988 p. 479-483).
When Ti is employed as a high-melting point metal material in the salicide-forming process, the heat treatment (2nd RTA) of not lower than 850° C. is required to be performed after the formation of metastable silicide (Ti5Si3 or TiSi2 (C49 phase)) at low temperatures (1st RTA) in order to form a normally stable silicide (TiSi2 (C54 phase)) layer (see for example, H. Kotaki, K. Mitsuhashi, J. Takagi, Y. Akagi and M. Koba; “Low Resistance and Thermally Stable Ti-Silicided Shallow Junction Formed by Advanced 2-Step Rapid Thermal Processing and Its Application to Deep Submicron Contact”; Jpn. J. Appl. Phys., Vol. 32, Part 1, No. 1B, January 1993, pp. 389-395). Further, in order to re-distribute the impurities doped in the Si thin film in a process of forming silicide on the Si thin film, it is generally required to carefully perform the silicide-forming process. In view of these embodiments, it is very important to carefully select a material which is well matched with the TFT-forming process from metallic materials and also carefully construct the TFT-forming process, since the performance of the end-device will be determined by these factors. Furthermore, in order to form excellent silicide, impurity oxygen existing in the gas to be used or inside the high-melting point metal should be thoroughly eliminated. Judging from the free energy in the production of oxide, most of the materials, excluding Ti and Zr, are smaller in free energy in the production of oxides thereof than that of Si, so that SiO2 is caused to be formed at the crystal interfaces during the heat treatment and hence various troubles such as conduction failures are expected to be generated. As described above, under the limited condition in temperature of 600° C., experimental data obtained therefrom are still insufficient, so that it is required to establish a novel process design by fundamentally re-examining the silicide-forming process (see for example, H. Kotaki, M. Nakano, S. Hayashida, S. Kakimoto, K. Mitsuhashi, and J. Takagi; “Novel Oxygen Free Titanium Silicidation (OFS) Processing for Low Resistance and Thermally Stable SALICIDE (Self-Aligned Silicide) in Deep Submicron Dual Gate CMOS (Complementary Metal-Oxide Semiconductors)”; Jpn. J. Appl. Phys., Vol. 34, Part 1, No. 2B, February 1995, pp. 776-781).
For example, in order to provide a flat panel display device with an enhanced function and an enhanced added value, it is required to enhance the crystallinity of the semiconductor thin film to be used as an active layer in a thin film transistor and to restore the original crystallinity that has been once turned into amorphous body due to the ion implantation (or ion doping) to thereby enhance the activation factor of the impurities implanted into the active layer. It is generally required for these purposes to increase the heat treatment temperature of the substrate and to take a sufficient heat treatment time.
However, in view of the aforementioned low heat resistance of the glass substrate (in other words, in view of the problem of the heat treatment characteristics of the existing glass substrate, especially the heat shrinkage thereof which may exceed an acceptable value of the alignment margin in the step of photolithography due to the increased fineness of pattern in recent years), it is difficult to apply a process of heat treatment of 600° C. or more to the manufacturing process of a high-performance thin film transistor. In addition to this problem as well as in order to enable a low cost substrate to be utilized, it is now demanded a novel process which makes it possible to further lower the heat treatment temperature.
Incidentally, at present, there is generally employed heat resistant glass (high strain-resisting glass) such as Corning 1737 or Asahi AN-100. Otherwise, a glass substrate is subjected to annealing to enhance the heat resistance of the glass substrate before use. Both of these measures lead to an increase in cost of manufacturing process.
Further, with regard to the heat treatment time, if the heat treatment is performed at low temperatures, the heat treatment time needed for the activation of impurities will be prolonged, thus making it unpractical in overcoming the aforementioned problem. Additionally, due to the recent trend to adopt a large size substrate, it is now increasingly difficult to employ a batch treatment (a system for reducing the heat treatment time per sheet of substrate by performing the heat treatment of a plurality of substrates at the same time). Namely, in the recent trend to employ single wafer processing and in viewpoints of manufacturing tact and apparatus cost in the single wafer processing, it is becoming increasingly difficult to cope with the aforementioned problems by making use of the conventional method. Additionally, in order to realize a highly refined image display, it is now indispensable to further increase the speed of image signals, i.e. to further decrease the electric resistance of the signal lines including the source/drain regions and the contact portion.
Further, in order to enhance the miniaturization of device, it is required to form a shallow impurity diffusion region and, at the same time, to reduce the parasitic resistance at the source/drain regions, which may be caused to increase as trade-off. For the purpose of reducing the parasitic resistance, it is desirable to form an impurity distribution having a high impurity concentration region at the surfaces thereof and a sharp inclination in impurity concentration at both vertical and lateral directions. In the field of developing the TFT technique, the thinning of layer in vertical direction, especially the thinning of the Si active layer has been advanced more increasingly than the trend of developing the LSI technique, so that it is difficult to realize the 0.5 μm rule TFT simply by making use of the technique that has been adopted in the 0.5 μm rule LSI technique.
Up to date, the formation of a shallow junction has been realized by the ion implantation of low acceleration and by the lowered process temperature. However, these countermeasures for forming the shallow junction are accompanied with persistent problems including the junction leakage due to the crystal defects that have been introduced by the ion implantation, and non-uniform growth of silicide film or junction breakdown especially when the aforementioned SALICIDE process is employed.